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串行数据链路分析 (SDLA)

信号频率加快和幅度变小为计算机、通信及内存总线的测试带来挑战。米乐m6网页版登录入口的高级串行数据链路分析解决方案可实现检定、一致性和调试工作之间的无缝过渡，加快产品上市时间。

SDLA Visualizer for MSO/DPO70000 Series Real Time Oscilloscopes : SDLA 可视化仪可实现完整的测量电路反嵌、模拟电路嵌入和接收机均衡。 SDLA 可视化仪带 DPOJET 抖动和眼图分析，为计算机、通信和内存总线提供完整的仿真和测量环境。

80SJNB 抖动、时序以及用于采样示波器的 SDLA 可视化仪链路分析 ：将 80SJNB 与 Tektronix DSA8300 采样示波器配合使用，可允许用户使用 SDLA 可视化仪和 DFE/FFE 均衡指定通道嵌入的反嵌滤波器、时域波形或 S 参数。80SJNB 分析软件还执行定时和噪声相关分析，获得眼图性能的 3D 视图，对于速度超过 50GHz 的信号进行深入、准确的评估。
MSO/DPO70000 系列实时示波器的 SignalCorrect™ 软件和 TCS70902 校准源 ：SignalCorrect™ 可以使用TCS70902 快速步进源及 DPO/MSO70000 系列实时示波器上捕获的响应，迅速分析电缆、夹具和其他类型互连的特点。基于这种检定功能，SignalCorrect 可以设计反嵌滤波器，补偿互连中的损耗，并提供平坦的响应，支持信号裕量恢复，使测量更准确。

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Correlation of Measurement and Simulation Results using IBIS-AMI Models on Measurement Instruments (DesignCon 2014) Introduction Increasing data rates have resulted in the requirement for post processing of data before measurements can be taken. This post processing typically involves de-embedding …
PCI Express Gen5 Automated Multi-Lane Testing Introduction Comprehensive characterization of high-speed links such as PCI Express® require performing measurements of the Transmitter (Tx) and Receiver (Rx) across multiple …
Validation & Analysis of Complex Serial Bus Link Models (DesignCon 2013) This paper highlights an application framework for performing serial data link modeling and analysis using live waveforms on a real-time oscilloscope. It then introduces a method for re-sampling S …
DesignCon 2015 文章 – 320 Gbit/s 背板系统的混合建模测量检定本文探讨一个难以完全测量和反嵌的多通道以太网背板 320 Gbit/s 系统案例研究，实现了建模、反嵌和测量的混合方法，探索度量方法的改进和结果的独立验证，并讨论在 28Gb/s 和 10Gb/s 速率条件下使用的方法。
采用80SJNB Advanced的均衡和串行数据链路分析方法(SDLA)应用指南本应用指南介绍了在有损耗或者耗散的信道上运行的串行数据标准使用的测试和测量方法，在接收端这些串行数据的眼图会呈现关闭状态，使用均衡(FFE/DFE)技术可以使眼图张开。在这里还将接收端上的测量数据与发送端上的建议测量数据作一些比较，以及串行数据设计人员和测试工程师感兴趣的其它SDLA概念。
串行数据链路分析 SDLA Visualizer软件为计算嵌入滤波器和反嵌滤波器、进行实时测量和仿真提供了全面的功能。本应用指南重点介绍嵌入和反嵌操作及测量实例。

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PCIe Gen5 Rx Calibration Listen as Joey Chiu, Tektronix PCI Express Applications Engineer, discusses PCI Express Gen5 Receiver (Rx) calibration. He covers how to prepare for it, what to expect, troubleshooting, and how to …
Using SDLA Visualizer Learn how to open closed eyes using equalization techniques and how to de-embed reflections and loss caused by the measurement setup using SDLA Visualizer for Tektronix Real-Time Oscilloscopes.
TDR Analysis for S Parameter Creation This webinar reviews TDR basics and the ability to create S-parameters using TDR/TDT measurements to validate high speed channels for debug or de-embedding in a Serial Data Link Analysis application.
PCI Express Gen 4 and Gen 5 Transmitter and Receiver Validation PCI Express I/O bandwidth has doubled every 3 years on average thereby leading to an increased demand for this full duplex high speed bus architecture. As the industry begins deploying the 5.0 …
How to Address Your Toughest Serial Bus Design Challenges with EDA and Measurement Correlation This Tektronix webinar will teach engineers how to use modeling tools to correlate simulations with high-speed physical layer measurements on Serial Bus Standards using the DPO/MSO70000 Series …
DDR5 Memory Characterization While they promise to provide datacenters with large amounts of data at faster speeds and lower power consumption, DDR5 memory devices have unique test challenges. Learn about characterization and …
Advanced Jitter and Noise Analysis As serial data speeds increase, the need to perform accurate timing and jitter measurements is key to staying current in your design role. Check out this new webinar that covers advances in the …

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